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From 5b64dc2000826365cff157de0bbeaedc21eb90d7 Mon Sep 17 00:00:00 2001
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| 2 |
From: Dave Airlie <airlied@redhat.com>
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| 3 |
Date: Fri, 3 Apr 2009 13:19:09 +1000
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Subject: [PATCH] drm: backwards compat layer on top of F11 DRM for F10
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| 5 |
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| 6 |
for radeon kms
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| 7 |
---
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| 8 |
drivers/gpu/drm/radeon/radeon_gem.c | 254 +++++++++++++++++++++++++++++++++++
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| 9 |
include/drm/drm.h | 39 +++---
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| 10 |
include/drm/drm_mode.h | 23 ++--
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| 11 |
include/drm/radeon_drm.h | 18 +++-
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| 12 |
4 files changed, 306 insertions(+), 28 deletions(-)
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| 13 |
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| 14 |
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
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| 15 |
index ab9c005..2fd1c5d 100644
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--- a/drivers/gpu/drm/radeon/radeon_gem.c
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+++ b/drivers/gpu/drm/radeon/radeon_gem.c
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| 18 |
@@ -30,6 +30,9 @@
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| 19 |
static int radeon_gem_ib_init(struct drm_device *dev);
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| 20 |
static int radeon_gem_ib_destroy(struct drm_device *dev);
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| 21 |
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| 22 |
+static int radeon_gem_dma_bufs_init(struct drm_device *dev);
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| 23 |
+static void radeon_gem_dma_bufs_destroy(struct drm_device *dev);
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| 24 |
+
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| 25 |
int radeon_gem_init_object(struct drm_gem_object *obj)
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| 26 |
{
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| 27 |
struct drm_radeon_gem_object *obj_priv;
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| 28 |
@@ -721,6 +724,7 @@ int radeon_alloc_gart_objects(struct drm_device *dev)
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| 29 |
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| 30 |
/* init the indirect buffers */
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| 31 |
radeon_gem_ib_init(dev);
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| 32 |
+ radeon_gem_dma_bufs_init(dev);
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| 33 |
return 0;
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| 34 |
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| 35 |
}
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@@ -1158,6 +1162,8 @@ void radeon_gem_mm_fini(struct drm_device *dev)
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| 37 |
{
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| 38 |
drm_radeon_private_t *dev_priv = dev->dev_private;
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| 39 |
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| 40 |
+ radeon_gem_dma_bufs_destroy(dev);
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| 41 |
+
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radeon_gem_ib_destroy(dev);
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mutex_lock(&dev->struct_mutex);
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@@ -1583,3 +1589,251 @@ void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master
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| 46 |
}
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| 47 |
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| 48 |
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| 49 |
+
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| 50 |
+#define RADEON_DMA_BUFFER_SIZE (64 * 1024)
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| 51 |
+#define RADEON_DMA_BUFFER_COUNT (16)
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+
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| 53 |
+
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+/**
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| 55 |
+ * Cleanup after an error on one of the addbufs() functions.
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| 56 |
+ *
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| 57 |
+ * \param dev DRM device.
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| 58 |
+ * \param entry buffer entry where the error occurred.
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| 59 |
+ *
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+ * Frees any pages and buffers associated with the given entry.
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+ */
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+static void drm_cleanup_buf_error(struct drm_device * dev,
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+ struct drm_buf_entry * entry)
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+{
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+ int i;
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+
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| 67 |
+ if (entry->seg_count) {
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+ for (i = 0; i < entry->seg_count; i++) {
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| 69 |
+ if (entry->seglist[i]) {
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+ drm_pci_free(dev, entry->seglist[i]);
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+ }
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+ }
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+ drm_free(entry->seglist,
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+ entry->seg_count *
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| 75 |
+ sizeof(*entry->seglist), DRM_MEM_SEGS);
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| 76 |
+
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| 77 |
+ entry->seg_count = 0;
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| 78 |
+ }
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| 79 |
+
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| 80 |
+ if (entry->buf_count) {
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| 81 |
+ for (i = 0; i < entry->buf_count; i++) {
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+ if (entry->buflist[i].dev_private) {
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+ drm_free(entry->buflist[i].dev_private,
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+ entry->buflist[i].dev_priv_size,
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+ DRM_MEM_BUFS);
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+ }
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+ }
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+ drm_free(entry->buflist,
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+ entry->buf_count *
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+ sizeof(*entry->buflist), DRM_MEM_BUFS);
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+
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+ entry->buf_count = 0;
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+ }
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+}
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+
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+static int radeon_gem_addbufs(struct drm_device *dev)
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+{
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+ struct drm_radeon_private *dev_priv = dev->dev_private;
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+ struct drm_device_dma *dma = dev->dma;
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+ struct drm_buf_entry *entry;
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+ struct drm_buf *buf;
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+ unsigned long offset;
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+ unsigned long agp_offset;
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+ int count;
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+ int order;
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+ int size;
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+ int alignment;
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+ int page_order;
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+ int total;
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+ int byte_count;
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+ int i;
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+ struct drm_buf **temp_buflist;
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+
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+ if (!dma)
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+ return -EINVAL;
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+
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+ count = RADEON_DMA_BUFFER_COUNT;
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+ order = drm_order(RADEON_DMA_BUFFER_SIZE);
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+ size = 1 << order;
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+
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+ alignment = PAGE_ALIGN(size);
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+ page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
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+ total = PAGE_SIZE << page_order;
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+
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+ byte_count = 0;
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+ agp_offset = dev_priv->mm.dma_bufs.bo->offset;
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+
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+ DRM_DEBUG("count: %d\n", count);
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+ DRM_DEBUG("order: %d\n", order);
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+ DRM_DEBUG("size: %d\n", size);
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+ DRM_DEBUG("agp_offset: %lu\n", agp_offset);
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+ DRM_DEBUG("alignment: %d\n", alignment);
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+ DRM_DEBUG("page_order: %d\n", page_order);
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+ DRM_DEBUG("total: %d\n", total);
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+
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+ if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER)
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+ return -EINVAL;
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+ if (dev->queue_count)
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+ return -EBUSY; /* Not while in use */
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+
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+ spin_lock(&dev->count_lock);
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+ if (dev->buf_use) {
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+ spin_unlock(&dev->count_lock);
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+ return -EBUSY;
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+ }
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+ atomic_inc(&dev->buf_alloc);
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+ spin_unlock(&dev->count_lock);
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+
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+ mutex_lock(&dev->struct_mutex);
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+ entry = &dma->bufs[order];
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+ if (entry->buf_count) {
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+ mutex_unlock(&dev->struct_mutex);
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+ atomic_dec(&dev->buf_alloc);
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+ return -ENOMEM; /* May only call once for each order */
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+ }
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+
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+ if (count < 0 || count > 4096) {
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+ mutex_unlock(&dev->struct_mutex);
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+ atomic_dec(&dev->buf_alloc);
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+ return -EINVAL;
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+ }
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+
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+ entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
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+ DRM_MEM_BUFS);
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+ if (!entry->buflist) {
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+ mutex_unlock(&dev->struct_mutex);
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+ atomic_dec(&dev->buf_alloc);
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+ return -ENOMEM;
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+ }
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+ memset(entry->buflist, 0, count * sizeof(*entry->buflist));
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+
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+ entry->buf_size = size;
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+ entry->page_order = page_order;
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+
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+ offset = 0;
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+
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+ while (entry->buf_count < count) {
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+ buf = &entry->buflist[entry->buf_count];
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+ buf->idx = dma->buf_count + entry->buf_count;
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+ buf->total = alignment;
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+ buf->order = order;
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+ buf->used = 0;
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+
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+ buf->offset = (dma->byte_count + offset);
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+ buf->bus_address = dev_priv->gart_vm_start + agp_offset + offset;
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+ buf->address = (void *)(agp_offset + offset);
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+ buf->next = NULL;
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+ buf->waiting = 0;
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+ buf->pending = 0;
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+ init_waitqueue_head(&buf->dma_wait);
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+ buf->file_priv = NULL;
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+
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+ buf->dev_priv_size = dev->driver->dev_priv_size;
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+ buf->dev_private = drm_alloc(buf->dev_priv_size, DRM_MEM_BUFS);
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+ if (!buf->dev_private) {
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+ /* Set count correctly so we free the proper amount. */
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+ entry->buf_count = count;
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+ drm_cleanup_buf_error(dev, entry);
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+ mutex_unlock(&dev->struct_mutex);
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+ atomic_dec(&dev->buf_alloc);
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+ return -ENOMEM;
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+ }
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+
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+ memset(buf->dev_private, 0, buf->dev_priv_size);
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+
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+ DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address);
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+
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+ offset += alignment;
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+ entry->buf_count++;
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+ byte_count += PAGE_SIZE << page_order;
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+ }
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+
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+ DRM_DEBUG("byte_count: %d\n", byte_count);
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+
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+ temp_buflist = drm_realloc(dma->buflist,
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+ dma->buf_count * sizeof(*dma->buflist),
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+ (dma->buf_count + entry->buf_count)
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+ * sizeof(*dma->buflist), DRM_MEM_BUFS);
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+ if (!temp_buflist) {
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+ /* Free the entry because it isn't valid */
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+ drm_cleanup_buf_error(dev, entry);
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+ mutex_unlock(&dev->struct_mutex);
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+ atomic_dec(&dev->buf_alloc);
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+ return -ENOMEM;
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+ }
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| 226 |
+ dma->buflist = temp_buflist;
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+
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+ for (i = 0; i < entry->buf_count; i++) {
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+ dma->buflist[i + dma->buf_count] = &entry->buflist[i];
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+ }
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+
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+ dma->buf_count += entry->buf_count;
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+ dma->seg_count += entry->seg_count;
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+ dma->page_count += byte_count >> PAGE_SHIFT;
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+ dma->byte_count += byte_count;
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+
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+ DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count);
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+ DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count);
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| 239 |
+
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| 240 |
+ mutex_unlock(&dev->struct_mutex);
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| 241 |
+
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| 242 |
+ dma->flags = _DRM_DMA_USE_SG;
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| 243 |
+ atomic_dec(&dev->buf_alloc);
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+ return 0;
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+}
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| 246 |
+
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| 247 |
+static int radeon_gem_dma_bufs_init(struct drm_device *dev)
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| 248 |
+{
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| 249 |
+ struct drm_radeon_private *dev_priv = dev->dev_private;
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| 250 |
+ int size = RADEON_DMA_BUFFER_SIZE * RADEON_DMA_BUFFER_COUNT;
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| 251 |
+ int ret;
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| 252 |
+
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| 253 |
+ ret = drm_dma_setup(dev);
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| 254 |
+ if (ret < 0)
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| 255 |
+ return ret;
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| 256 |
+
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| 257 |
+ ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
|
| 258 |
+ DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_NO_EVICT |
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| 259 |
+ DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_MAPPABLE, 0,
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+ 0, 0, &dev_priv->mm.dma_bufs.bo);
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| 261 |
+ if (ret) {
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| 262 |
+ DRM_ERROR("Failed to create DMA bufs\n");
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+ return -ENOMEM;
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| 264 |
+ }
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| 265 |
+
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+ ret = drm_bo_kmap(dev_priv->mm.dma_bufs.bo, 0, size >> PAGE_SHIFT,
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+ &dev_priv->mm.dma_bufs.kmap);
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| 268 |
+ if (ret) {
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| 269 |
+ DRM_ERROR("Failed to mmap DMA buffers\n");
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| 270 |
+ return -ENOMEM;
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| 271 |
+ }
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+ dev_priv->mm.gart_useable -= size;
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+ DRM_DEBUG("\n");
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| 274 |
+ radeon_gem_addbufs(dev);
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+
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| 276 |
+ DRM_DEBUG("%lx %d\n", dev_priv->mm.dma_bufs.bo->map_list.hash.key, size);
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+ dev->agp_buffer_token = dev_priv->mm.dma_bufs.bo->map_list.hash.key << PAGE_SHIFT;
|
| 278 |
+ dev_priv->mm.fake_agp_map.handle = dev_priv->mm.dma_bufs.kmap.virtual;
|
| 279 |
+ dev_priv->mm.fake_agp_map.size = size;
|
| 280 |
+
|
| 281 |
+ dev->agp_buffer_map = &dev_priv->mm.fake_agp_map;
|
| 282 |
+ dev_priv->gart_buffers_offset = dev_priv->mm.dma_bufs.bo->offset + dev_priv->gart_vm_start;
|
| 283 |
+ return 0;
|
| 284 |
+}
|
| 285 |
+
|
| 286 |
+static void radeon_gem_dma_bufs_destroy(struct drm_device *dev)
|
| 287 |
+{
|
| 288 |
+
|
| 289 |
+ struct drm_radeon_private *dev_priv = dev->dev_private;
|
| 290 |
+ drm_dma_takedown(dev);
|
| 291 |
+
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| 292 |
+ if (dev_priv->mm.dma_bufs.bo) {
|
| 293 |
+ drm_bo_kunmap(&dev_priv->mm.dma_bufs.kmap);
|
| 294 |
+ drm_bo_usage_deref_unlocked(&dev_priv->mm.dma_bufs.bo);
|
| 295 |
+ }
|
| 296 |
+}
|
| 297 |
diff --git a/include/drm/drm.h b/include/drm/drm.h
|
| 298 |
index 17a1e2c..fa02570 100644
|
| 299 |
--- a/include/drm/drm.h
|
| 300 |
+++ b/include/drm/drm.h
|
| 301 |
@@ -671,23 +671,28 @@ struct drm_gem_open {
|
| 302 |
|
| 303 |
#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
|
| 304 |
|
| 305 |
-#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
|
| 306 |
-#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
|
| 307 |
-#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
|
| 308 |
-#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
|
| 309 |
-#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
|
| 310 |
-#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
|
| 311 |
-#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
|
| 312 |
-#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
|
| 313 |
-#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
|
| 314 |
-#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
|
| 315 |
-
|
| 316 |
-#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
|
| 317 |
-#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
|
| 318 |
-#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
|
| 319 |
-#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
|
| 320 |
-#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
|
| 321 |
-#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
|
| 322 |
+#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
|
| 323 |
+#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
|
| 324 |
+#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA2, struct drm_mode_get_connector)
|
| 325 |
+#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA3, struct drm_mode_crtc)
|
| 326 |
+#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xA4, struct drm_mode_fb_cmd)
|
| 327 |
+#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xA5, unsigned int)
|
| 328 |
+#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xA6, struct drm_mode_fb_cmd)
|
| 329 |
+
|
| 330 |
+#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xA7, struct drm_mode_connector_set_property)
|
| 331 |
+#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xA8, struct drm_mode_get_blob)
|
| 332 |
+#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
|
| 333 |
+#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xAA, struct drm_mode_mode_cmd)
|
| 334 |
+
|
| 335 |
+#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAB, struct drm_mode_get_property)
|
| 336 |
+#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xAC, struct drm_mode_cursor)
|
| 337 |
+#define DRM_IOCTL_MODE_HOTPLUG DRM_IOWR(0xAD, struct drm_mode_hotplug)
|
| 338 |
+#define DRM_IOCTL_WAIT_HOTPLUG DRM_IOWR(0xAE, union drm_wait_hotplug)
|
| 339 |
+
|
| 340 |
+#define DRM_IOCTL_MODE_REPLACEFB DRM_IOWR(0xAF, struct drm_mode_fb_cmd)
|
| 341 |
+#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xB0, struct drm_mode_get_encoder)
|
| 342 |
+#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xB1, struct drm_mode_crtc_lut)
|
| 343 |
+#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xB2, struct drm_mode_crtc_lut)
|
| 344 |
|
| 345 |
/**
|
| 346 |
* Device specific ioctls should only be in their respective headers
|
| 347 |
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
|
| 348 |
index 601d2bd..58417e5 100644
|
| 349 |
--- a/include/drm/drm_mode.h
|
| 350 |
+++ b/include/drm/drm_mode.h
|
| 351 |
@@ -126,10 +126,11 @@ struct drm_mode_crtc {
|
| 352 |
#define DRM_MODE_ENCODER_TVDAC 4
|
| 353 |
|
| 354 |
struct drm_mode_get_encoder {
|
| 355 |
- uint32_t encoder_id;
|
| 356 |
- uint32_t encoder_type;
|
| 357 |
|
| 358 |
- uint32_t crtc_id; /**< Id of crtc */
|
| 359 |
+ unsigned int encoder_type;
|
| 360 |
+ unsigned int encoder_id;
|
| 361 |
+
|
| 362 |
+ unsigned int crtc_id; /**< Id of crtc */
|
| 363 |
|
| 364 |
uint32_t possible_crtcs;
|
| 365 |
uint32_t possible_clones;
|
| 366 |
@@ -216,13 +217,15 @@ struct drm_mode_get_blob {
|
| 367 |
};
|
| 368 |
|
| 369 |
struct drm_mode_fb_cmd {
|
| 370 |
- uint32_t fb_id;
|
| 371 |
- uint32_t width, height;
|
| 372 |
- uint32_t pitch;
|
| 373 |
- uint32_t bpp;
|
| 374 |
- uint32_t depth;
|
| 375 |
- /* driver specific handle */
|
| 376 |
- uint32_t handle;
|
| 377 |
+ union {
|
| 378 |
+ unsigned int fb_id;
|
| 379 |
+ unsigned int buffer_id;
|
| 380 |
+ };
|
| 381 |
+ unsigned int width, height;
|
| 382 |
+ unsigned int pitch;
|
| 383 |
+ unsigned int bpp;
|
| 384 |
+ unsigned int handle;
|
| 385 |
+ unsigned int depth;
|
| 386 |
};
|
| 387 |
|
| 388 |
struct drm_mode_mode_cmd {
|
| 389 |
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
|
| 390 |
index f716e0a..d6a233f 100644
|
| 391 |
--- a/include/drm/radeon_drm.h
|
| 392 |
+++ b/include/drm/radeon_drm.h
|
| 393 |
@@ -514,7 +514,8 @@ typedef struct {
|
| 394 |
#define DRM_RADEON_GEM_SET_DOMAIN 0x23
|
| 395 |
#define DRM_RADEON_GEM_WAIT_RENDERING 0x24
|
| 396 |
|
| 397 |
-#define DRM_RADEON_CS 0x26
|
| 398 |
+#define DRM_RADEON_CS 0x26
|
| 399 |
+#define DRM_RADEON_CS2 0x26
|
| 400 |
|
| 401 |
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
|
| 402 |
#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
|
| 403 |
@@ -554,6 +555,7 @@ typedef struct {
|
| 404 |
#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
|
| 405 |
#define DRM_IOCTL_RADEON_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_RENDERING, struct drm_radeon_gem_wait_rendering)
|
| 406 |
#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
|
| 407 |
+#define DRM_IOCTL_RADEON_CS2 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS2, struct drm_radeon_cs2)
|
| 408 |
|
| 409 |
|
| 410 |
typedef struct drm_radeon_init {
|
| 411 |
@@ -869,6 +871,14 @@ struct drm_radeon_gem_pwrite {
|
| 412 |
|
| 413 |
/* New interface which obsolete all previous interface.
|
| 414 |
*/
|
| 415 |
+
|
| 416 |
+
|
| 417 |
+struct drm_radeon_cs_old {
|
| 418 |
+ uint32_t dwords;
|
| 419 |
+ uint32_t cs_id;
|
| 420 |
+ uint64_t packets;
|
| 421 |
+};
|
| 422 |
+
|
| 423 |
#define RADEON_CHUNK_ID_RELOCS 0x01
|
| 424 |
#define RADEON_CHUNK_ID_IB 0x02
|
| 425 |
#define RADEON_CHUNK_ID_OLD 0xff
|
| 426 |
@@ -886,5 +896,11 @@ struct drm_radeon_cs {
|
| 427 |
cs chunks */
|
| 428 |
};
|
| 429 |
|
| 430 |
+struct drm_radeon_cs2 {
|
| 431 |
+ uint32_t num_chunks;
|
| 432 |
+ uint32_t cs_id;
|
| 433 |
+ uint64_t chunks; /* this points to uint64_t * which point to
|
| 434 |
+ cs chunks */
|
| 435 |
+};
|
| 436 |
|
| 437 |
#endif
|
| 438 |
--
|
| 439 |
1.6.0.6
|
| 440 |
|
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